1. Technical Field
The present disclosure relates to analog-to-digital converters (ADCs) and, more particularly, to an ADC utilizing a capacitor array during multiple conversion stages and amplifier sharing across multiple lanes.
2. Description of Related Art
Analog-to-digital converters (ADCs) are utilized in many products and applications requiring conversion of an analog signal into digital signal. For example, ADCs are a critical component of both wideband and narrowband communication receivers. In such applications, power consumption and area requirements may impose practical limitations on ADC resolution and/or architecture.
The resolution quality of an ADC is often specified by an effective number of bits (ENOB), which is the number of bits representing an input signal, excluding the number of bits representing noise. In traditional ADC architectures, such as pipeline ADCs for example, the ENOB may be limited by kT/C noise to ˜10b at multi-GS/s rates without relatively high power consumption. Further, conventional pipeline ADCs may take several steps before the first quantization step, in which input signal sampling, a sample-and-hold amplifier and a first multiplying digital-to-analog (MDAC) stage may all contribute noise and distortion. Some techniques to reduce these steps require splitting of a clock period, which may limit the sample rate of an ADC. Other techniques to reduce these steps involve auxiliary circuitry which may add design complexities and increase power consumption.